1. Field of the Invention
This invention relates to integrated circuit packaging technology, and more particularly, to a stacked multi-chip package structure with on-chip integration of passive component that allows the overall package construction to be made more compact in size.
2. Description of Related Art
Multi-chip packaging technology is used to pack two or more semiconductor chips in one single package module, so that one single package module is capable of offering a manifold level of functionality or data storage capacity. Memory chips, such as flash memory chips, are typically packaged in this way so as to allow one single memory module to offer an increased level of data storage capacity.
In some applications, such as high-frequency semiconductor devices, it is often required to integrate passive components, such as resistors, inductors, and capacitors, with the packaged semiconductor chips so as to make the integrated circuitry meet specific electrical requirements. Conventionally, these passive components are mounted on a remaining area of the substrate that is unoccupied by the packaged semiconductor chips. This layout scheme, however, would make the overall package construction considerably large in size.
Related patents, include, for example, the U.S. Pat. No. 5,633,785 entitled xe2x80x9cINTEGRATED CIRCUIT COMPONENT PACKAGE WITH INTEGRAL PASSIVE COMPONENTxe2x80x9d. This patent teaches the use of an interconnect substrate that is integrally formed with passive components therein. This passive component integration scheme, however, has the following drawbacks. First, it requires an extra substrate area/for accommodating the passive components, which would make the overall package construction considerably large in size. Second, it would make the substrate more complex in structure, making the overall packaging process more laborious and costly to implement.
It is therefore an objective of this invention to provide a stacked multi-chip package structure, which can integrate passive components in the package without having to use an extra substrate area so that the overall package construction can be made more compact in size than prior art.
It is another objective of this invention to provide a stacked multi-chip package structure, which can use off-the-shelf passive components for integration with the packaged semiconductor chips, while nonetheless allowing the overall package construction to be made more compact in size than prior art.
In accordance with the foregoing and other objectives, the invention proposes a stacked multi-chip package structure with on-chip integration of passive component.
Broadly recited; the stacked multi-chip package structure of the invention comprises (a) a substrate; (b) a first semiconductor chip mounted over the substrate; (c) a second semiconductor chip mounted over the first semiconductor chip; the second semiconductor chip being smaller in size than the first semiconductor chip; and (d) at least one passive component mounted beside the second semiconductor chip and over the first semiconductor chip.
In the foregoing stacked multi-chip package structure, the first semiconductor chip and the second semiconductor chip can be mounted by means of adhesive layers or flip-chip technology. The passive component can be electrically coupled to the semiconductor chips through the use of wire-bonding technology (WBT) or surface-mount technology (SMT).
Since the passive component is mounted on a remaining surface area of the first semiconductor chip that is unoccupied by the second semiconductor chip, rather than over the substrate, it allows the overall package construction to be made more compact in size than the prior art.